In computer and electronic device operations, flash memory and similar non-volatile memory can provides great advantages in the maintenance of data, providing low power operation with low cost and high density. Because data is stored in a compact format that requires minimal power in operation and does not require power to maintain storage, such memory is being used in increasing numbers of applications.
However, non-volatile memory has certain downsides in operation. For example, memory such as flash memory has a limited lifespan in use because such memory tends to deteriorate with each write cycle. For this reason, if a certain portion of the memory is subject to more write operations than other portions of the memory, then the portions with a greater number of writes will tend to deteriorate and ultimately fail more quickly.
In order to lengthen the overall lifespan of flash memory, a wear leveling process may be implemented. The wear leveling process is intended to more evenly distribute the wear over the storage device by directing write operations to less heavily used portions of the memory. This process may be handled by the memory controller, with the host system being unaware of the process.
Wear leveling may include an algorithm for re-mapping logical block addresses to different physical block addresses in the device's solid-state memory array.
However, the algorithm used can greatly affect the efficiency of memory operation and the effectiveness of the wear leveling process. Issues such as the timing of re-mapping processes, the manner in which the appropriate physical areas are identified for re-mapping, and related issues can greatly affect memory operation.